Values for the 4 programmable delays associated with SDRAM operation.
| CMDDLY | Programmable delay value for EMC outputs in command delayed mode. See Section 9.12.6. The delay amount is roughly (CMDDLY+1) * 250 picoseconds. This field applies only when the command delayed read strategy is selected in the EMCDynamicReadConfig register. In this mode, all control outputs from the EMC are delayed, but the output clock is not. Delaying the control outputs changes dynamic characteristics defined in the device data sheet. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| FBCLKDLY | Programmable delay value for the feedback clock that controls input data sampling. See Section 9.5.3. The delay amount is roughly (FBCLKDLY+1) * 250 picoseconds. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| CLKOUT0DLY | Programmable delay value for the CLKOUT0 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT0DLY+1) * 250 picoseconds. Delaying the clock output changes dynamic characteristics defined in the device data sheet. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| CLKOUT1DLY | Programmable delay value for the CLKOUT1 output. This would typically be used in clock delayed mode. See Section 9.12.6 The delay amount is roughly (CLKOUT1DLY+1) * 250 picoseconds. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |